(1) Field of the Invention
The invention relates to a method of planarizing an integrated circuit device, and more particularly, to a method of planarizing a submicron integrated circuit device by integrating a partial etchback siloxane process with a silicate process.
(2) Description of the Prior Art
In conventional planarization of the metallurgy-dielectric layers of an integrated circuit, a metal is deposited and patterned by conventional lithography and etching techniques. Then the dielectric layer, which is typically silicon oxide material, is formed thereover. The dielectric layer may now be etched back to planarize the metallurgy-dielectric layers. There are basic problems in the choice of thickness of the dielectric layer. The problems occur particularly where there are substantially different heights on the surfaces of the integrated circuit, particularly in the formation of memory word lines and the like in memory products. For example, in the areas where contact is planned to be made to the patterned metal, it is desired to have a thick dielectric layer to keep planarity, but the thick dielectric will cause voids in other areas. Alternatively, if a thin dielectric layer is used, there is lost planarity in the contact area and etchback encroachment of the metal pattern, but there will not be a void problem in other surface areas of the integrated circuit. There is not a good solution for this planarity versus void surface problem in the art.
The spin-on-glass materials have been used for planarization of integrated circuits. The material to be applied is thoroughly mixed in a suitable solvent. The spin-on-glass material suspended in the vehicle or solvent is deposited onto the semiconductor wafer surface and uniformly spread thereover by the action of spinning the wafer. The material fills the indentations in the integrated circuit wafer surface, that is planarization. Most of the vehicle or solvent is dirven off by a low temperature baking step often followed by vacuum degassing. Other coatings of the spin-on-glass material are applied, baked and vacuum degassed until the desired spin-on-glass layer is formed.
The final step in the making of the spin-on-glass layer is curing. Curing is a high temperature heating step to cause the breakdown of the silicate or siloxane material to a silicon dioxide like cross linked material.
In the conventional sandwich process, a conformal oxide is first deposited followed by a double coat of a phosphorus-doped silicate spin-on-glass material. This is cured at about 425.degree. C. to become a phosphorus-doped silicon dioxide. The final oxide of the sandwich is deposited. This process can result in cracks and the planarity is poor. This process cannot be scaled down to the submicron level because there may be cracks in the small spaces and poor planarity in the wide spaces.
In the conventional etchback process, a siloxane spin-on-glass layer is etched back resulting in a poisoned via metallurgy, such as aluminum, caused by outgassing. When a via opening is made through the spin-on-glass, leaving a portion of the spin-on-glass exposed, there may be outgassing of water from the spin-on-glass layer. This water reacts with the aluminum causing corrosion of the aluminum. This method also cannot be scaled down to the submicron size because voids will occur where the first silicon oxide layer is very thick. If, however, the first silicon oxide layer is thin, planarity will be lost during etchback for the reasons described above.
A number of patents have addressed these and other problems in spin-on-glass planarization. U.S. Pat. No. 5,003,062 to Yen involves a sandwich process in which the spin-on-glass material can be either silicate or siloxane. A vacuum degassing step is used. In U.S. Pat. No. 4,775,550 to Chu et al, the first insulating layer is very thick, on the order of 8000 to 10,000 Angstroms. This thickness causes voids in the submicron area. The aforementioned patent to Chu et al as well as U.S. Pat. Nos. 4,676,867 to Elkins et al and 4,885,262 to Ting et al each show spin-on-glass etchback processes with use of a sandwich dielectric. Japanese publications 2-65256 (A), 63-302537 (A), 1-241135 (A), 2-1912 (A), 1-303741 (A), and 2-26054 (A) all show various processes for siloxane and silicate spin-on-glass.